Zhu Shien

Appointment: PhD student

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61 to 70 of 189 Results

STTCiM-test1-AND.png Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks PNG Image - 322.3 KB - MD5: a576506e8c1d1f88a58e04b3d01c0783
STTCiM-test1-In30p-Out.png Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks PNG Image - 1.2 MB - MD5: 559f20245c4187489e38fd114035ec48
STTCiM-test2-2021-8-13.png Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks PNG Image - 330.2 KB - MD5: 10ea7d2166a0132eed51c5ff4c101199
STTCiM-test2-Cin-Cout.png Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks PNG Image - 1.2 MB - MD5: 739c89a59512700701936f095d7a765d
STTCiM-test2-In30p-Cout.png Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks PNG Image - 373.8 KB - MD5: e9f99a3a85be21b8619f99199cefb622
STTCiM-test2-In30p-Out.png Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks PNG Image - 1.2 MB - MD5: 51e1352c7d0b108ff4edb1eb2b66d4e7
STTCiM-test3-2021-8-14.png Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks PNG Image - 1.4 MB - MD5: 37c99eea00b2648f70faae49e8eee851
STTCiM-test3-In30p-Out.png Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks PNG Image - 1.2 MB - MD5: 70f084469facc4cb78c0e2b76873a4fe
STTCiM-test4-2021-8-14.png Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks PNG Image - 1.2 MB - MD5: 9710c8b7331a074aae24c923a72ef707
Replication Data for: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations May 12, 2022 Zhu, Shien; Li, Shiqing; Liu, Weichen, 2022, "Replication Data for: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations", https://doi.org/10.21979/N9/JNFW9P, DR-NTU (Data), V2, UNF:6:L3+xW/BxBE6fYNWBm4ta6Q== [fileUNF] The simulation code, experiment results, and graphs used in the GLSVLSI 2022 paper: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations

STTCiM-test1-AND.png

Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

PNG Image - 322.3 KB -

STTCiM-test1-In30p-Out.png

Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

PNG Image - 1.2 MB -

STTCiM-test2-2021-8-13.png

Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

PNG Image - 330.2 KB -

STTCiM-test2-Cin-Cout.png

Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

PNG Image - 1.2 MB -

STTCiM-test2-In30p-Cout.png

Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

PNG Image - 373.8 KB -

STTCiM-test2-In30p-Out.png

Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

PNG Image - 1.2 MB -

STTCiM-test3-2021-8-14.png

Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

PNG Image - 1.4 MB -

STTCiM-test3-In30p-Out.png

Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

PNG Image - 1.2 MB -

STTCiM-test4-2021-8-14.png

Dec 14, 2023 - Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

PNG Image - 1.2 MB -

Replication Data for: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations

May 12, 2022

Zhu, Shien; Li, Shiqing; Liu, Weichen, 2022, "Replication Data for: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations", https://doi.org/10.21979/N9/JNFW9P, DR-NTU (Data), V2, UNF:6:L3+xW/BxBE6fYNWBm4ta6Q== [fileUNF]

The simulation code, experiment results, and graphs used in the GLSVLSI 2022 paper: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations

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