Zhu Shien

Appointment: PhD Student

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1 to 5 of 5 Results

Replication Data for: iMAT: Energy-Efficient In-Memory Acceleration of Ternary Neural Networks With Sparse Dot Product Dec 18, 2023 Zhu, Shien; Huai, Shuo; Xiong, Guochu; Liu, Weichen, 2023, "Replication Data for: iMAT: Energy-Efficient In-Memory Acceleration of Ternary Neural Networks With Sparse Dot Product", https://doi.org/10.21979/N9/B4SIIN, DR-NTU (Data), V1, UNF:6:KboaxJ9ZX4FgcAqcXn8SqQ== [fileUNF] This dataset contains the simulation environment, simulation results, and post-processing data for the iMAT paper published in ISLPED 2023.
Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks Dec 14, 2023 Zhu, Shien; Duong, H. K. Luan; Chen, Hui; Di, Liu; Liu, Weichen, 2023, "Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks", https://doi.org/10.21979/N9/DYKUPV, DR-NTU (Data), V1, UNF:6:UCCl9ySs+IN5trVkl2AGQQ== [fileUNF] This dataset contains the codes, figures, and tables for the TCAD 2022 paper: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks.
Replication Data for: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations May 12, 2022 Zhu, Shien; Li, Shiqing; Liu, Weichen, 2022, "Replication Data for: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations", https://doi.org/10.21979/N9/JNFW9P, DR-NTU (Data), V2, UNF:6:L3+xW/BxBE6fYNWBm4ta6Q== [fileUNF] The simulation code, experiment results, and graphs used in the GLSVLSI 2022 paper: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations
Replication Data for: TAB: Unified and Optimized Ternary, Binary and Mixed-Precision Neural Network Inference on the Edge May 10, 2022 Zhu, Shien; Duong, H. K. Luan; Liu, Weichen, 2022, "Replication Data for: TAB: Unified and Optimized Ternary, Binary and Mixed-Precision Neural Network Inference on the Edge", https://doi.org/10.21979/N9/RZ75BY, DR-NTU (Data), V1, UNF:6:Md7is6scgmHZ4O3PtUuAOg== [fileUNF] The TAB experiment code running on ARM CPU, x86 CPU, and Nvidia GPU.
Replication Data for: XOR-Net: An Efficient Computation Pipeline for Binary Neural Network Inference on Edge Devices Dec 21, 2020 Zhu, Shien; Duong, H. K. Luan; Liu, Weichen, 2020, "Replication Data for: XOR-Net: An Efficient Computation Pipeline for Binary Neural Network Inference on Edge Devices", https://doi.org/10.21979/N9/XEH3D1, DR-NTU (Data), V1, UNF:6:5DOBB66c624HMnkRD7Qw9g== [fileUNF] Accepted as a conference paper by IEEE International Conference on Parallel and Distributed Systems (ICPADS) 2020.

Replication Data for: iMAT: Energy-Efficient In-Memory Acceleration of Ternary Neural Networks With Sparse Dot Product

Dec 18, 2023

Zhu, Shien; Huai, Shuo; Xiong, Guochu; Liu, Weichen, 2023, "Replication Data for: iMAT: Energy-Efficient In-Memory Acceleration of Ternary Neural Networks With Sparse Dot Product", https://doi.org/10.21979/N9/B4SIIN, DR-NTU (Data), V1, UNF:6:KboaxJ9ZX4FgcAqcXn8SqQ== [fileUNF]

This dataset contains the simulation environment, simulation results, and post-processing data for the iMAT paper published in ISLPED 2023.

Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

Dec 14, 2023

Zhu, Shien; Duong, H. K. Luan; Chen, Hui; Di, Liu; Liu, Weichen, 2023, "Replication Data for: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks", https://doi.org/10.21979/N9/DYKUPV, DR-NTU (Data), V1, UNF:6:UCCl9ySs+IN5trVkl2AGQQ== [fileUNF]

This dataset contains the codes, figures, and tables for the TCAD 2022 paper: FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks.

Replication Data for: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations

May 12, 2022

Zhu, Shien; Li, Shiqing; Liu, Weichen, 2022, "Replication Data for: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations", https://doi.org/10.21979/N9/JNFW9P, DR-NTU (Data), V2, UNF:6:L3+xW/BxBE6fYNWBm4ta6Q== [fileUNF]

The simulation code, experiment results, and graphs used in the GLSVLSI 2022 paper: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations

Replication Data for: TAB: Unified and Optimized Ternary, Binary and Mixed-Precision Neural Network Inference on the Edge

May 10, 2022

Zhu, Shien; Duong, H. K. Luan; Liu, Weichen, 2022, "Replication Data for: TAB: Unified and Optimized Ternary, Binary and Mixed-Precision Neural Network Inference on the Edge", https://doi.org/10.21979/N9/RZ75BY, DR-NTU (Data), V1, UNF:6:Md7is6scgmHZ4O3PtUuAOg== [fileUNF]

The TAB experiment code running on ARM CPU, x86 CPU, and Nvidia GPU.

Replication Data for: XOR-Net: An Efficient Computation Pipeline for Binary Neural Network Inference on Edge Devices

Dec 21, 2020

Zhu, Shien; Duong, H. K. Luan; Liu, Weichen, 2020, "Replication Data for: XOR-Net: An Efficient Computation Pipeline for Binary Neural Network Inference on Edge Devices", https://doi.org/10.21979/N9/XEH3D1, DR-NTU (Data), V1, UNF:6:5DOBB66c624HMnkRD7Qw9g== [fileUNF]

Accepted as a conference paper by IEEE International Conference on Parallel and Distributed Systems (ICPADS) 2020.

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