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61 to 70 of 70 Results
Example_Mesh8x8_AIR1_improved.json
Dec 5, 2023 - Related data for: Thermal-aware task mapping on dynamically reconfigurable networkon- chip based multiprocessor system-on-chip
JSON - 6.4 KB - MD5: 3287128c83a5bb541ff8bc2819824830
NoC.patch
Dec 5, 2023 - Related data for: Thermal-aware task mapping on dynamically reconfigurable networkon- chip based multiprocessor system-on-chip
Unknown - 273.3 KB - MD5: 718b6087b43dd527031b53ae2c1dd13a
README.md
Dec 5, 2023 - Related data for: Thermal-aware task mapping on dynamically reconfigurable networkon- chip based multiprocessor system-on-chip
Markdown Text - 4.0 KB - MD5: 625f1865a14c0d73d485dc401291f008
Documentation
Related Data for: Efficient FPGA-based sparse matrix-vector multiplication with data reuse-aware compression
Sep 20, 2023
Li, Shiqing; Liu, Di; Liu, Weichen, 2023, "Related Data for: Efficient FPGA-based sparse matrix-vector multiplication with data reuse-aware compression", https://doi.org/10.21979/N9/EXZ0Y3, DR-NTU (Data), V1
The code for the paper: Efficient FPGA-based sparse matrix-vector multiplication with data reuse-aware compression
Replication Data for: An efficient gustavson-based sparse matrix-matrix multiplication accelerator on embedded FPGAs
Sep 20, 2023
Li, Shiqing; Huai, Shuo; Liu, Weichen, 2023, "Replication Data for: An efficient gustavson-based sparse matrix-matrix multiplication accelerator on embedded FPGAs", https://doi.org/10.21979/N9/RKPHSM, DR-NTU (Data), V1
The code for the paper entitled An efficient gustavson-based sparse matrix-matrix multiplication accelerator on embedded FPGAs.
Related data for: Accelerating gustavson-based SpMM on embedded FPGAs with element-wise parallelism and access pattern-aware caches
Jun 14, 2023
Li, Shiqing; Liu, Weichen, 2023, "Related data for: Accelerating gustavson-based SpMM on embedded FPGAs with element-wise parallelism and access pattern-aware caches", https://doi.org/10.21979/N9/OA7NLF, DR-NTU (Data), V1
The code for our DATE work entitled "Accelerating Gustavson-based SpMM on embedded FPGAs with element-wise parallelism and access pattern-aware caches".
Related data for: Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes
Mar 30, 2023
Chen, Peng; Liu, Weichen, 2023, "Related data for: Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes", https://doi.org/10.21979/N9/JGBX4G, DR-NTU (Data), V1
The related code for the paper.
mapping.cpp
Mar 30, 2023 - Related data for: Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes
C++ Source - 3.1 KB - MD5: 93225c4cda6521abb5ad77894d7c67d2
routing.cpp
Mar 30, 2023 - Related data for: Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes
C++ Source - 25.7 KB - MD5: ab1085b542a05032277c39610847592d
Related data for:Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs
Mar 26, 2022
Li, Shiqing; Liu, Weichen, 2022, "Related data for:Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs", https://doi.org/10.21979/N9/ATEYFB, DR-NTU (Data), V1
This dataset is related to our ICCAD work "Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs".
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