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Design validation tool for CMOS-NVM
Design validation tool for CMOS-NVM
Feb 20, 2020
Wang, Yuhao; Ni, Leibin; Chang, Chiphong; Yu, Hao, 2020, "Design validation tool for CMOS-NVM", https://doi.org/10.21979/N9/ETYMHM, DR-NTU (Data), V1
NVMspice is introduced based on recent new modified nodal analysis (MNA) framework, which can effectively support the non-conventional state variables. As such, NVM devices can be stamped into state matrix similarly as one BSIM MOSFET. Compared with equivalent circuit simulation...
NVMspice_linux_32_bit.tar.gz
Feb 20, 2020 - Design validation tool for CMOS-NVM
Gzip Archive - 2.1 MB - MD5: 3cc5b716fa5df6e4d197485bc2d9861c
32bit library for nvmspice
NVMspice_linux_64_bit.tar.gz
Feb 20, 2020 - Design validation tool for CMOS-NVM
Gzip Archive - 2.4 MB - MD5: 659df1de1cc3a3ce7202816da0cb6144
64bit library for nvmspice
nvmspice.source.tar.gz
Feb 20, 2020 - Design validation tool for CMOS-NVM
Gzip Archive - 6.9 MB - MD5: d0cce92628681916b987afacab48ef23
source code for nvmspice
nvmspice_tool.pdf
nvmspice_tool.pdf
Feb 20, 2020 - Design validation tool for CMOS-NVM
Adobe PDF - 210.3 KB - MD5: 7c688f23ef3be0121ae8aa84ddd89157
A Quick Guide for NVMspice
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