Related Data for: Efficient FPGA-based sparse matrix-vector multiplication with data reuse-aware compression (doi:10.21979/N9/EXZ0Y3)

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Part 2: Study Description
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Document Description

Citation

Title:

Related Data for: Efficient FPGA-based sparse matrix-vector multiplication with data reuse-aware compression

Identification Number:

doi:10.21979/N9/EXZ0Y3

Distributor:

DR-NTU (Data)

Date of Distribution:

2023-09-20

Version:

1

Bibliographic Citation:

Li, Shiqing; Liu, Di; Liu, Weichen, 2023, "Related Data for: Efficient FPGA-based sparse matrix-vector multiplication with data reuse-aware compression", https://doi.org/10.21979/N9/EXZ0Y3, DR-NTU (Data), V1

Study Description

Citation

Title:

Related Data for: Efficient FPGA-based sparse matrix-vector multiplication with data reuse-aware compression

Identification Number:

doi:10.21979/N9/EXZ0Y3

Authoring Entity:

Li, Shiqing (Nanyang Technological University)

Liu, Di (Norwegian University of Science and Technology)

Liu, Weichen (Nanyang Technological University)

Software used in Production:

Vivado

Grant Number:

MOE2019-T2-1-071

Grant Number:

NAP (M4082282/04INS000515C130)

Distributor:

DR-NTU (Data)

Access Authority:

Li, Shiqing

Depositor:

Li, Shiqing

Date of Deposit:

2023-09-20

Holdings Information:

https://doi.org/10.21979/N9/EXZ0Y3

Study Scope

Keywords:

Engineering, Engineering, FPGA, Sparse matrix-verctor Multiplication

Abstract:

The code for the paper: Efficient FPGA-based sparse matrix-vector multiplication with data reuse-aware compression

Kind of Data:

Code

Methodology and Processing

Sources Statement

Data Access

Other Study Description Materials

Related Studies

The related data files and documentation are published at Github: <a href="https://github.com/lsq314/SpMV_ICCAD">https://github.com/lsq314/SpMV_ICCAD</a>

Related Publications

Citation

Identification Number:

10.1109/TCAD.2023.3281715

Bibliographic Citation:

Li, S., Liu, D., & Liu, W. (2023). Efficient FPGA-based Sparse Matrix-Vector Multiplication with Data Reuse-aware Compression. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Citation

Identification Number:

10356/169152

Bibliographic Citation:

Li, S., Liu, D., & Liu, W. (2023). Efficient FPGA-based Sparse Matrix-Vector Multiplication with Data Reuse-aware Compression. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.