Understanding Charge-Trapping Evolution In Small-Dimension Logic/Memory Devices (MOE2016-T2-2-102) (doi:10.21979/N9/GP2AUB)

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Part 2: Study Description
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Document Description

Citation

Title:

Understanding Charge-Trapping Evolution In Small-Dimension Logic/Memory Devices (MOE2016-T2-2-102)

Identification Number:

doi:10.21979/N9/GP2AUB

Distributor:

DR-NTU (Data)

Date of Distribution:

2022-05-20

Version:

1

Bibliographic Citation:

Ang, Diing Shenp, 2022, "Understanding Charge-Trapping Evolution In Small-Dimension Logic/Memory Devices (MOE2016-T2-2-102)", https://doi.org/10.21979/N9/GP2AUB, DR-NTU (Data), V1

Study Description

Citation

Title:

Understanding Charge-Trapping Evolution In Small-Dimension Logic/Memory Devices (MOE2016-T2-2-102)

Identification Number:

doi:10.21979/N9/GP2AUB

Authoring Entity:

Ang, Diing Shenp (Nanyang Technological University)

Software used in Production:

Origin

Grant Number:

MOE2016-T2-2-102

Distributor:

DR-NTU (Data)

Access Authority:

Ang, Diing Shenp

Depositor:

Ang, Diing Shenp

Date of Deposit:

2022-05-20

Holdings Information:

https://doi.org/10.21979/N9/GP2AUB

Study Scope

Keywords:

Engineering, Engineering, metal-oxide-semiconductor field-effect transistor, gate dielectric traps, channel hot-carrier effect, bias-temperature instability

Abstract:

Measurement data compilation for the project.

Kind of Data:

Measurement data

Methodology and Processing

Sources Statement

Data Access

Notes:

Please contact the PI to request for access.

Other Study Description Materials

Other Study-Related Materials

Label:

Data(1).pptx

Notes:

application/vnd.openxmlformats-officedocument.presentationml.presentation

Other Study-Related Materials

Label:

Data(2).pptx

Notes:

application/vnd.openxmlformats-officedocument.presentationml.presentation