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Part 1: Document Description
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Citation |
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Title: |
Replication Data for: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations |
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Identification Number: |
doi:10.21979/N9/JNFW9P |
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Distributor: |
DR-NTU (Data) |
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Date of Distribution: |
2022-05-10 |
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Version: |
2 |
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Bibliographic Citation: |
Zhu, Shien; Li, Shiqing; Liu, Weichen, 2022, "Replication Data for: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations", https://doi.org/10.21979/N9/JNFW9P, DR-NTU (Data), V2, UNF:6:L3+xW/BxBE6fYNWBm4ta6Q== [fileUNF] |
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Citation |
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Title: |
Replication Data for: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations |
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Identification Number: |
doi:10.21979/N9/JNFW9P |
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Authoring Entity: |
Zhu, Shien (Nanyang Technological University) |
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Li, Shiqing (Nanyang Technological University) |
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Liu, Weichen (Nanyang Technological University) |
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Software used in Production: |
Cadence IC Virtuoso |
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Grant Number: |
Academic Research Fund Tier 2 MOE2019-T2- 1-071 |
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Grant Number: |
Academic Research Fund Tier 1 MOE2019-T1-001-072 |
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Grant Number: |
NAP M4082282 |
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Grant Number: |
SUG M4082087 |
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Distributor: |
DR-NTU (Data) |
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Access Authority: |
Zhu Shien |
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Depositor: |
Zhu Shien |
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Date of Deposit: |
2022-04-14 |
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Holdings Information: |
https://doi.org/10.21979/N9/JNFW9P |
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Study Scope |
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Keywords: |
Computer and Information Science, Computer and Information Science, Adder Neural Network, In-Memory Computing |
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Abstract: |
The simulation code, experiment results, and graphs used in the GLSVLSI 2022 paper: iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations |
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Kind of Data: |
Simulation source code |
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Kind of Data: |
Experiment result record |
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Methodology and Processing |
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Sources Statement |
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Data Access |
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Other Study Description Materials |
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Related Publications |
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Citation |
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Identification Number: |
10.1145/3526241.3530313 |
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Bibliographic Citation: |
Zhu, S., Li, S., & Liu, W. (2022, June). iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations. In Proceedings of the Great Lakes Symposium on VLSI 2022 (pp. 65-70). |
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Citation |
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Identification Number: |
10356/156404 |
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Bibliographic Citation: |
Zhu, S., Li, S., & Liu, W. (2022, June). iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations. In Proceedings of the Great Lakes Symposium on VLSI 2022 (pp. 65-70). |
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File Description--f87505 |
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File: iMAD Simulation Results.tab |
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Notes: |
UNF:6:L3+xW/BxBE6fYNWBm4ta6Q== |
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List of Variables: | |
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Variables |
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f87505 Location: |
Variable Format: character Notes: UNF:6:nB59jj1Y4tLEhrbseMCaDw== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:E4Y+bliFhF/JoezPjnG0eQ== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:D6EWwFCTCDJwQWyl/Cw88Q== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:SxSFOdVy69gtX4LxPHAHjw== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:PeDKMq8reP26KiekkyUtmQ== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:St4Eau8uAP94yIv5Krtu1Q== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:9/K8UbID4YN1g38NlZHp/A== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:UwQNoE5x0YC3S1VV+7d06Q== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:GsJWctaqLwP9EmxnSHNfww== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:J7yJ9giSYJ8F6qMAL9Qd6w== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:obqalKxNkGmhmayhuB5JXg== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:C3BcnaYjx0AVtjdntVG3WA== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:y7rXRjXZtQV6RfmsEw2u1g== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:TCLUTn7ifWYhD+hBAn2f8w== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:ubQx8gPwsNO4eotWDQB3Fw== |
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f87505 Location: |
Variable Format: character Notes: UNF:6:o6fyyS96sfpsOfFgVwCfzA== |
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Label: |
CAPIM-00s11_voltage-08-10_SL-10-04_MUX8.png |
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Notes: |
image/png |
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Label: |
CAPIM-11a00_voltage-08-10_SL-071-04_MUX8.png |
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Notes: |
image/png |
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Label: |
CAPIM-11s00_voltage-08-10_SL-08-04_MUX8.png |
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Notes: |
image/png |
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Label: |
Dir-00s00_voltage-08-10_SL-08-04_MUX4.png |
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Notes: |
image/png |
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Label: |
Dir-00s11_voltage-08-10_SL-08-06_MUX4.png |
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Notes: |
image/png |
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Label: |
Dir-11a00_voltage-08-10_SL-07-04_MUX4.png |
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Notes: |
image/png |
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Label: |
Dir-11s00_voltage-08-10_SL-10-06_MUX4.png |
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Notes: |
image/png |
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Label: |
FAT-00s00_voltage-08-10_SL-08-06_MUX4.png |
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Notes: |
image/png |
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Label: |
FAT-00s11_voltage-08-10_SL-10-04_MUX4-carry.png |
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Notes: |
image/png |
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Label: |
FAT-11a00_voltage-08-10_SL-07-04_MUX4.png |
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Notes: |
image/png |
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Label: |
FAT-11a01_voltage-08-10_SL-07-06_MUX4.png |
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Notes: |
image/png |
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Label: |
FAT-11s00_voltage-08-10_SL-08-07_MUX4.png |
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Notes: |
image/png |
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Label: |
iMAD.drawio |
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Text: |
The iMAD architecture graphs in the paper. |
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Notes: |
application/octet-stream |
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Label: |
MRIMA-00s11_voltage-08-10_SL-10-04_MUX8.png |
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Notes: |
image/png |
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Label: |
MRIMA-11a00_voltage-08-10_SL-07-04_MUX8-carry.png |
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Notes: |
image/png |
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Label: |
MRIMA-11a00_voltage-08-10_SL-07-04_MUX8.png |
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Notes: |
image/png |
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Label: |
MRIMA-11s00_voltage-08-10_SL-08-07_MUX8.png |
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Notes: |
image/png |
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Label: |
TRS-00s00_voltage-08-10_SL-08-04_MUX4-TGSel2.png |
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Notes: |
image/png |
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Label: |
TRS-00s11_voltage-08-10_SL-08-06_MUX4-TGSel2.png |
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Notes: |
image/png |
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Label: |
TRS-11a00_voltage-08-10_SL-073-04_MUX4-TGSel2-5ns.png |
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Notes: |
image/png |
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Label: |
TRS-11s00_voltage-08-10_SL-08-06_MUX4-TGSel2-carry.png |
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Notes: |
image/png |
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Label: |
Virtuoso Simulation.zip |
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Text: |
The simulation code with a README.md |
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Notes: |
application/zip |